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HD74LS174 / HD74LS175
Hex / Quadruple D-type Flip-Flops (with clear)
REJ03D0451-0300 Rev.3.00 Jul.15.2005 These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the HD74LS175 features complementary outputs from each flip-flops. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the outputs.
Features
* Ordering Information * HD74LS174
Part Name HD74LS174P HD74LS174FPEL HD74LS174RPEL Package Type DILP-16 pin SOP-16 pin (JEITA) SOP-16 pin (JEDEC) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) PRSP0016DH-B (FP-16DAV) PRSP0016DG-A (FP-16DNV) Package Abbreviation P FP RP Taping Abbreviation (Quantity) -- EL (2,000 pcs/reel) EL (2,500 pcs/reel)
* HD74LS175
Part Name HD74LS175P HD74LS175FPEL HD74LS175RPEL Package Type DILP-16 pin SOP-16 pin (JEITA) SOP-16 pin (JEDEC) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) PRSP0016DH-B (FP-16DAV) Package Abbreviation P FP Taping Abbreviation (Quantity) -- EL (2,000 pcs/reel) EL (2,500 pcs/reel)
PRSP0016DG-A RP (FP-16DNV) Note: Please consult the sales office for the above package availability.
Rev.3.00, Jul.15.2005, page 1 of 8
HD74LS174 / HD74LS175
Pin Arrangement
HD74LS174 HD74LS175
Clear 1Q 1D 2D 2Q 3D 3Q GND
1 2 3 4 5 6 7 8
Q CLR D CK Q CLR CK D
16 15 14 13 12 11 10 9
VCC 6Q 6D 5D 5Q 4D 4Q Clock
Clear 1Q 1Q 1D 2D 2Q 2Q GND
1 2 3 4 5 6 7 8
Q D CK Q CLR Q D CK CLR Q Q CLR CK Q D CLR Q CK D Q
16 15 14 13 12 11 10 9
VCC 4Q 4Q 4D 3D 3Q 3Q Clock
D CK CLR Q
CK D CLR Q
D CK CLR Q
CK D CLR Q
(Top view)
(Top view)
Function Table
Clear L H H H Notes: 1. 2. 3. 4. Inputs Clock X L Outputs D X H L X Q L H L Q0 Q H L H Q0
H; high level, L; low level, X; irrelevant ; transition from low to high level Q0; the level of Q before the indicated steady-state input conditions were established. Q is applied to HD74LS175 only.
Rev.3.00, Jul.15.2005, page 2 of 8
HD74LS174 / HD74LS175
Block Diagram
HD74LS174 HD74LS175
1D
D CK
Q
1Q
1D
D CK
Q
1Q 1Q
Clear
Q Clear
2D
D CK
Q
2Q 2D
D CK
Q
2Q 2Q Outputs
Clear Data Inputs 3D D CK Clear Q 3Q Outputs 3D
Q Clear
Data Inputs
D CK
Q
3Q 3Q
Q Clear 4D D CK Clear Clock D CK Clear Q 5Q Clear 4D D CK Q Clear Q Q 4Q
4Q 4Q
5D
6D
D CK
Q
6Q
Clock Clear
Clear
Absolute Maximum Ratings
Item Supply voltage Input voltage Power dissipation Storage temperature Symbol VCC VIN PT Tstg Ratings 7 7 400 -65 to +150 Unit V V mW C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Rev.3.00, Jul.15.2005, page 3 of 8
HD74LS174 / HD74LS175
Recommended Operating Conditions
* HD74LS174
Item Supply voltage Output current Operating temperature Clock frequency Clock pulse width Clear pulse width Data input Setup time Data hold time Clear inactivestate Symbol VCC IOH IOL Topr clock tw (CK) tw (CLR) tsu (data) tsu (CLR) th (data) Min 4.75 -- -- -20 0 20 20 20 25 5 Typ 5.00 -- -- 25 -- -- -- -- -- -- Max 5.25 -400 8 75 30 -- -- -- -- -- Unit V A mA C MHz ns ns ns ns ns
* HD74LS175
Item Supply voltage Output current Operating temperature Clock frequency Clock pulse width Clear pulse width Data input Setup time Data hold time Clear inactivestate Symbol VCC IOH IOL Topr clock tw (CK) tw (CLR) tsu (data) tsu (CLR) th (data) Min 4.75 -- -- -20 0 20 20 20 25 5 Typ 5.00 -- -- 25 -- -- -- -- -- -- Max 5.25 -400 8 75 30 -- -- -- -- -- Unit V A mA C MHz ns ns ns ns ns
Electrical Characteristics
(Ta = -20 to +75 C)
Item Input voltage Symbol VIH VIL VOH Output voltage VOL IIH IIL II Short-circuit output current Supply current** IOS ICC min. 2.0 -- 2.7 -- -- -- -- -- -20 -- -- -- typ.* -- -- -- -- -- -- -- -- -- 16 11 -- max. -- 0.8 -- 0.5 0.4 20 -0.4 0.1 -100 26 18 -1.5 Unit V V V V A mA mA mA mA Condition
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = -400 A IOL = 8 mA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V IOL = 4 mA VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V VCC = 5.25 V HD74LS174 VCC = 5.25 V HD74LS175 VCC = 4.75 V, IIN = -18 mA
Input current
Input clamp voltage VIK V Notes: * VCC = 5 V, Ta = 25C ** With all outputs open and 4.5 V applied to all data and cleat inputs, ICC is measured after a momentary grounded, then 4.5 V, is applied to clock.
Rev.3.00, Jul.15.2005, page 4 of 8
HD74LS174 / HD74LS175
Switching Characteristics
* HD74LS174 (VCC = 5 V, Ta = 25C)
Item Maximum clock frequency Propagation delay time Symbol max tPHL tPLH tPHL Inputs Clock Clear Clock Clock Outputs Q Q Q Q min. 30 -- -- -- typ. 40 23 20 21 max. -- 35 30 30 Unit MHz ns Condition CL = 15 pF, RL = 2 k
* HD74LS175 (VCC = 5 V, Ta = 25C)
Item Maximum clock frequency Symbol max tPLH tPHL tPLH tPHL Inputs Clock Clear Clock Clock Outputs Q, Q Q Q Q, Q Q, Q min. 30 -- -- -- -- typ. 40 16 20 13 16 max. -- 25 30 25 25 Unit MHz Condition
Propagation delay time
ns
CL = 15 pF, RL = 2 k
Testing Method
Test Circuit
VCC Out
In P.G. Zout = 50 Q
Load circuit 1 RL D
See Testing Table
CL
In P.G. Zout = 50
CK Out CLR Q Same as Load Circuit 1.
Notes:
1. Test is put into the each flip-flop. 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074(H).
Testing Table
Item max tPLH tPHL From input to output CKQ, Q* CKQ, Q* CLR 4.5 V 4.5 V IN Inputs CK IN IN IN Outputs D IN IN 4.5 V Q OUT Q OUT
CLRQ, Q* Note: *. HD74LS175 only
Rev.3.00, Jul.15.2005, page 5 of 8
HD74LS174 / HD74LS175 Waveform
tTHL tw (CLR) tTLH
3V
1.3V
CLR
1.3V tTLH 90% 90% 10% 10% tTHL
0V
tsu (CLR) t w (CK) tw (CK)
3V CK
1.3V 1.3V tsu th tsu 1.3V 1.3V
0V
th
3V D
tPHL 1.3V tPLH 1.3V tPHL 1.3V
0V VOH Q
1.3V tPLH tPHL 1.3V 1.3V
VOL
tPLH
VOH Q
(HD74LS175 only) 1.3V 1.3V 1.3V
VOL
Note:
Input pulse; tTLH 15 ns, tTHL 6 ns, PRR = 1 MHz, and: for max, tTLH = tTHL 2.5 ns.
Rev.3.00, Jul.15.2005, page 6 of 8
HD74LS174 / HD74LS175
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
E
A1
A
Reference Symbol
Dimension in Millimeters Min Nom 7.62 19.2 6.3 20.32 7.4 5.06 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 1.12 2.54 0.56 Max
e D E
L
1
A A1
e
bp
e1
b c b c
p 3
e Z ( Ni/Pd/Au plating ) L
JEITA Package Code P-SOP16-5.5x10.06-1.27
RENESAS Code PRSP0016DH-B
Previous Code FP-16DAV
MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
Reference Symbol
*2
c
Dimension in Millimeters Min Nom 10.06 5.50 Max 10.5
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c
0.00
0.10
0.20 2.20
0.34
0.40
0.46
0.15
1
0.20
0.25
A
c
HE
0 7.50 7.80 1.27
8 8.00
A1
y L
e x y
0.12 0.15 0.80 0.50
1
Detail F
Z L L 0.70 1.15
0.90
Rev.3.00, Jul.15.2005, page 7 of 8
HD74LS174 / HD74LS175
JEITA Package Code P-SOP16-3.95x9.9-1.27 RENESAS Code PRSP0016DG-A Previous Code FP-16DNV MASS[Typ.] 0.15g
*1
D 9
F
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
Index mark
*2
E
HE
c
Reference Symbol
Dimension in Millimeters Min Nom 9.90 3.95 Max 10.30
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c c
1
0.10
0.14
0.25 1.75
0.34
0.40
0.46
0.15
0.20
0.25
HE
0 5.80 6.10 1.27
8 6.20
A
A1
L y
e x y
0.25 0.15 0.635 0.40
1
Detail F
Z L L 0.60 1.08
1.27
Rev.3.00, Jul.15.2005, page 8 of 8
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